The invention relates to static timing analysis (STA) in particular to STA with improved accuracy, in particular improved accuracy with respect to graph-based static timing analysis (GBA), and improved efficiency, in particular improved efficiency with respect to path-based static timing analysis (PBA).
Current integrated circuit, IC, designs, may include an extremely large number of cells such as logic gates and synchronous or sequential devices connected by interconnects. The synchronous or sequential devices include flip-flops and latches.
STA, for example, in the course of electronic design automation (EDA) is tasked with analyzing a circuit design to determine if timing constraints are met, for example whether all timing signals arrive at constrained cells or interconnects of the circuit design within a respective required time. The difference between arrival and required time may be measured as slack, wherein a negative slack means an arrival time of the respective timing signal violates the respective required time and may lead to unstable circuit behavior. Designers may have to ensure that there are no violating or negative slacks in the design in order to sign-off the design.
GBA may determine slack values with linear complexity in the size of the circuit. GBA may combine information from different timing paths which may lead to overestimation of delays and hence a pessimistic slack. This may unfortunately lead to an overestimation in the number of violating paths in the circuit design.
PBA may analyze each timing path in isolation. Unfortunately, analyzing all timing paths is a problem of exponential complexity in the size of the circuit. Thus, performing PBA on an entire circuit may be infeasible for large circuits due to a large runtime and/or memory overhead.